Invention Grant
- Patent Title: Coverage model enhancement to support logic and arithmetic expressions
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Application No.: US16830248Application Date: 2020-03-25
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Publication No.: US10885252B1Publication Date: 2021-01-05
- Inventor: Rodion Vladimirovich Melnikov , Amit Metodi , Samer Raed Alqassis
- Applicant: Cadence Design Systems, Inc.
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G06F30/3323
- IPC: G06F30/3323 ; G06F30/31 ; G06F111/04 ; G06F119/12

Abstract:
Aspects of the present disclosure address systems and methods for functional coverage in integrated circuit (IC) designs utilizing arbitrary expression to define irrelevant domains in coverage item definitions. A coverage item definition is determined to include an arbitrary expression that defines an irrelevant domain for a coverage item in a functional coverage analysis of an IC design. Based on determining if the item definition comprises the arbitrary expression, a verification the arbitrary expression satisfies one or more analyzability conditions is performed. Based on verifying the arbitrary expression satisfies the one or more analyzability conditions, the irrelevant domain for the coverage item is calculated based on the arbitrary expression. An enhanced functional coverage model that excludes the irrelevant domain for the coverage item is generated and used to perform the functional coverage analysis on the IC design.
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