An existing layout of an Integrated Circuit (IC) is migrated to two or more target layouts for different semiconductor processes with different design rules. The existing layout file is parsed for data items such as boundaries, paths, text, and cell instances to generate a layout database file with a text format. A layout engineer selects functions from a layout design toolkit and writes reusable code with these functions. Placement functions can specify relative locations to other data items that are dependent on the design rules. Routing functions allow interconnect to be re-routed after placements are adjusted for various target design rules. An analog layout expertise integrator replaces some of the data items in the layout database file with the reusable code to generate a reusable layout database. A layout generator compiles the reusable layout database and converts it to multiple target layouts for multiple design rules.