Self-aligned interconnect patterning for back-end-of-line (BEOL) structures is described. A method of fabricating an interconnect structure for an integrated circuit includes depositing a first metal layer on an initial interconnect structure, forming a patterned spacer layer containing recessed features on the first metal layer, and etching a self-aligned via in the first metal layer and into the initial interconnect structure using a recessed feature in the patterned spacer layer as a mask. The method further includes filling the via in the first metal layer and the recessed features in the patterned spacer layer with a second metal layer, removing the patterned spacer layer, and etching a recessed feature in the first metal layer using the second metal layer as a mask.