Invention Grant
- Patent Title: Methods and systems for wafer bonding alignment compensation
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Application No.: US16736689Application Date: 2020-01-07
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Publication No.: US10886256B2Publication Date: 2021-01-05
- Inventor: Shuai Guo
- Applicant: Yangtze Memory Technologies Co., Ltd.
- Applicant Address: CN Hubei
- Assignee: Yangtze Memory Technologies Co., Ltd.
- Current Assignee: Yangtze Memory Technologies Co., Ltd.
- Current Assignee Address: CN Hubei
- Agency: Sterne, Kessler, Goldstein & Fox P.L.L.C.
- Main IPC: H01L25/065
- IPC: H01L25/065 ; B81C3/00 ; H01L21/66 ; H01L23/544 ; H01L25/00

Abstract:
Embodiments of methods and systems for wafer bonding alignment compensation are disclosed. The method comprises bonding a first pair of wafers including a first wafer and a second wafer, wherein the first pair of wafers have a plurality of corresponding bonding alignment mark pairs each including a first bonding alignment mark on the first wafer and a second bonding alignment mark on the second wafer; measuring alignment positions of the plurality of bonding alignment mark pairs; determining a mean run-out misalignment between the first pair of wafers using the alignment measurement, wherein the mean run-out misalignment indicates a deformation of at least one of the first pair of wafers; and during bonding of a second pair of wafers, controlling a wafer deformation adjustment module to compensate for the run-out misalignment based on the mean run-out misalignment of the first pair of wafers.
Public/Granted literature
- US20200219850A1 Methods and Systems for Wafer Bonding Alignment Compensation Public/Granted day:2020-07-09
Information query
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