Forming FinFET with reduced variability
Abstract:
A semiconductor structure is provided that includes active semiconductor fins that have a uniform fin channel height. The uniform fin channel height is achieved by forming semiconductor fins (active and sacrificial) on an entirety of semiconductor substrate thus there is no loading effect during a subsequently performed dielectric etch step which can lead to fin channel height variation and ultimately variation in device characteristics. A trench isolation structure is located adjacent to the active semiconductor fins. The trench isolation structure includes at least one dielectric plug having a second width and a dielectric pillar having a first width located on each side of the at least one dielectric plug. The second width of the at least one dielectric plug is less than the first width of each dielectric pillar, yet equal to a width of each semiconductor fin.
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