Invention Grant
- Patent Title: Selective and direct deposition technique for streamlined CMOS processing
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Application No.: US16229838Application Date: 2018-12-21
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Publication No.: US10886452B2Publication Date: 2021-01-05
- Inventor: Sang H. Choi , Adam J. Duzik
- Applicant: UNITED STATES OF AMERICA AS REPRESENTED BY THE ADMINISTRATOR OF NASA
- Applicant Address: US DC Washington
- Assignee: UNITED STATES OF AMERICA AS REPRESENTED BY THE ADMINISTRATOR OF NASA
- Current Assignee: UNITED STATES OF AMERICA AS REPRESENTED BY THE ADMINISTRATOR OF NASA
- Current Assignee Address: US DC Washington
- Agent Shawn P. Gorman; Jennifer L. Riley; Helen M. Gaius
- Main IPC: H01L35/34
- IPC: H01L35/34 ; H01L35/30 ; H01L35/32 ; C23C14/14 ; H01L27/16 ; C23C14/04 ; H01L35/20

Abstract:
Systems, methods, and devices of the various embodiments provide for microfabrication of devices, such as semiconductors, thermoelectric devices, etc. Various embodiments may include a method for fabricating a device, such as a semiconductor (e.g., a silicon (Si)-based complementary metal-oxide-semiconductor (CMOS), etc.), thermoelectric device, etc., using a mask. In some embodiments, the mask may be configured to allow molecules in a deposition plume to pass through one or more holes in the mask. In some embodiments, molecules in a deposition plume may pass around the mask. Various embodiments may provide thermoelectric devices having metallic junctions. Various embodiments may provide thermoelectric devices having metallic junctions rather than junctions formed from semiconductors.
Public/Granted literature
- US20190229251A1 SELECTIVE AND DIRECT DEPOSITION TECHNIQUE FOR STREAMLINED CMOS PROCESSING Public/Granted day:2019-07-25
Information query
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