Invention Grant
- Patent Title: Sample-hold circuit and AD converter
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Application No.: US16570379Application Date: 2019-09-13
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Publication No.: US10886939B2Publication Date: 2021-01-05
- Inventor: Naoya Waki
- Applicant: Kabushiki Kaisha Toshiba , Toshiba Electronic Devices & Storage Corporation
- Applicant Address: JP Tokyo; JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba,Toshiba Electronic Devices & Storage Corporation
- Current Assignee: Kabushiki Kaisha Toshiba,Toshiba Electronic Devices & Storage Corporation
- Current Assignee Address: JP Tokyo; JP Tokyo
- Agency: White & Case LLP
- Priority: JP2019-050984 20190319
- Main IPC: H03M1/00
- IPC: H03M1/00 ; H03M3/00

Abstract:
According to an embodiment, a sample-hold circuit according to this embodiment is made up of a first device having a first withstand voltage and a second device having a second withstand voltage lower than the first withstand voltage. The sample-hold circuit includes a first switch element, a first capacitor, a second switch element, a third switch element, and a fourth switch element. The first switch element has the first withstand voltage. The first switch element operates upon receiving a first signal output from the device having the first withstand voltage. The second switch element has the first withstand voltage. The third switch element has the second withstand voltage. The fourth switch element has the second withstand voltage.
Public/Granted literature
- US20200304140A1 SAMPLE-HOLD CIRCUIT AND AD CONVERTER Public/Granted day:2020-09-24
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