Invention Grant
- Patent Title: Efficient decoding of n-dimensional error correction codes
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Application No.: US16228256Application Date: 2018-12-20
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Publication No.: US10886947B2Publication Date: 2021-01-05
- Inventor: Paul Edward Hanham , David Malcolm Symons , Francesco Giorgio
- Applicant: Toshiba Memory Corporation
- Applicant Address: JP Tokyo
- Assignee: Toshiba Memory Corporation
- Current Assignee: Toshiba Memory Corporation
- Current Assignee Address: JP Tokyo
- Agency: Foley & Lardner LLP
- Main IPC: H03M13/29
- IPC: H03M13/29 ; G06F11/10 ; G11C29/52

Abstract:
Various implementations are directed to systems and methods for maintaining integrity and reliability of data in an SSD device using error correction coding. According to certain aspects, for frames of data having an ECC code with two or more sub-codes, while one sub-decoder is not in use it could be used to start a decode of another frame. By “interleaving” and alternating the frames between sub-decoders, two or more frames can be decoded simultaneously in an efficient manner. This can clearly be extended to more sub-codes (i.e. dimensions greater than two).
Information query
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