Disclosed approaches for processing a circuit design include providing access to checkpoint data of a design checkpoint of a circuit design and starting child processes by a parent process. An initial intermediate representation is generated by the parent process, and concurrent with the generating of the initial intermediate representation, the child processes load the checkpoint data into respective memory spaces. The parent process produces incremental updates to the design checkpoint. The parent process signals availability of the incremental updates to the child processes, which apply the incremental updates to the checkpoint data in the respective memory spaces. The child processes process the circuit design in response to completion of producing incremental updates by the parent placer process.