Invention Grant
- Patent Title: High-bandwidth STO bias architecture with integrated slider voltage potential control
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Application No.: US16816211Application Date: 2020-03-11
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Publication No.: US10891973B2Publication Date: 2021-01-12
- Inventor: John Contreras , Yunfei Ding , Kuok San Ho , Ian Robson McFadyen , Joey Martin Poss
- Applicant: Western Digital Technologies, Inc.
- Applicant Address: US CA San Jose
- Assignee: Western Digital Technologies, Inc.
- Current Assignee: Western Digital Technologies, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Jacobsen IP Law
- Main IPC: G11B5/02
- IPC: G11B5/02 ; G11B5/09

Abstract:
Disclosed herein are circuits, architectures, and methods that provide for the control of a data storage device write head's trailing shield and main pole potential with respect to the disk using circuitry that is integrated with circuitry used to bias a spin torque oscillator (STO) apparatus. Various embodiments include slider connections with STO bias circuitry that resides in a read/write integrated circuit, which has a programmable circuit that generates a bias current with overshoot (bias kicks). Also disclosed are circuits that may be incorporated into a slider to mitigate radio-frequency interference.
Public/Granted literature
- US20200211584A1 HIGH-BANDWIDTH STO BIAS ARCHITECTURE WITH INTEGRATED SLIDER VOLTAGE POTENTIAL CONTROL Public/Granted day:2020-07-02
Information query
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