A memory device include write leveling circuitry that is configured to receive a write command from the command interface. The write leveling circuitry also receives a data strobe (DQS) signal from a host device (e.g., processor) and receives a clock signal from the host device. The write leveling circuitry also compares phases of the DQS signal and the clock signal using a phase detector. The write leveling circuitry also generates an internal write signal (IWS) based upon the write command, and outputs a captured result of a write leveling operation based at least in part on the compared phases and the IWS.