A method for manufacturing a vertical transistor device includes forming a first plurality of fins in a first device region on a substrate, and forming a second plurality of fins in a second device region on the substrate. In the method, a plurality of dummy gate layers are formed on the substrate and around portions of each of the first and second plurality of fins in the first and second device regions. A barrier layer is formed between the first and second device regions. More specifically, the barrier layer is formed between respective gate regions of the first and second device regions. The method also includes removing the plurality of dummy gate layers from the first and second device regions, and replacing the removed plurality of dummy gate layers with a plurality of gate metal layers in the first and second device regions.