A nonvolatile memory structure includes a substrate, a select transistor, and a floating-gate transistor. The substrate includes an oxide defined (OD) region and an erase region. The select transistor is disposed on the OD region, and the floating-gate transistor is disposed on the OD region between the select transistor and the erase region, wherein the floating gate has an extended portion capacitively coupled to the erase region, and the extended portion has an extending direction parallel to a first direction. The OD region further has an addition region protruding in a second direction and partially overlapped with the floating gate, in which the second direction is vertical to the first direction.