Invention Grant
- Patent Title: Gate insulating layer having a plurality of silicon oxide layer with varying thickness
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Application No.: US16558958Application Date: 2019-09-03
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Publication No.: US10892332B2Publication Date: 2021-01-12
- Inventor: Shigeto Fukatsu , Masaru Furukawa , Hiroshi Kono , Takuma Suzuki , Shunsuke Asaba
- Applicant: Kabushiki Kaisha Toshiba , Toshiba Electronic Devices & Storage Corporation
- Applicant Address: JP Tokyo; JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba,Toshiba Electronic Devices & Storage Corporation
- Current Assignee: Kabushiki Kaisha Toshiba,Toshiba Electronic Devices & Storage Corporation
- Current Assignee Address: JP Tokyo; JP Tokyo
- Agency: White & Case LLP
- Priority: JP2019-049192 20190315
- Main IPC: H01L31/0256
- IPC: H01L31/0256 ; H01L21/02 ; H01L21/00 ; H01L21/336 ; H01L29/16 ; H01L29/78 ; H01L29/51 ; H01L21/76 ; H01L29/66 ; H01L51/05

Abstract:
A semiconductor device according to an embodiment includes a silicon carbide layer; a gate electrode; and a gate insulating layer which is provided between the silicon carbide layer and the gate electrode and includes a first silicon oxide layer and a second silicon oxide layer provided between the first silicon oxide layer and the gate electrode, the first silicon oxide layer having a first nitrogen concentration and a first thickness, the second silicon oxide layer having a second nitrogen concentration lower than the first nitrogen concentration and a second thickness. The second thickness between an end portion of the gate electrode and the silicon carbide layer is greater than the second thickness between a central portion of the gate electrode and the silicon carbide layer.
Public/Granted literature
- US20200295140A1 SEMICONDUCTOR DEVICE Public/Granted day:2020-09-17
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