A system includes a pseudo-differential clock path configured to convey a first clock signal and a second clock signal, wherein the second clock signal is inverted relative to the first clock signal. The system also includes a sensing circuit coupled to sensing nodes of the pseudo-differential clock path. The sensing circuit is configured to provide a sense signal based on a comparison of the first clock signal and the second clock signal at the sensing nodes. The system also includes a correction circuit coupled to the sensing circuit and to adjustment nodes of the pseudo-differential clock path. The correction circuit is configured to adjust the first clock signal and the second clock signal using digital-to-analog converters (DACs) and the sense signal.