Various example embodiments relate to unifying a plurality of parallel interfaces. A transmitting apparatus configured to serialize parallel bits implements a dynamic divider circuit for loading varying parallel bits into the transmitting apparatus. An input clock generator is configured to generate a desired and/or predefined clock frequency. The dynamic divider circuit receives the desired and/or predefined clock frequency and generates a parallel clock frequency by dividing the desired and/or predefined clock frequency based on a variable division input. Number of parallel bits loaded into the transmitting apparatus is based on the generated parallel clock frequency. Further, a shift register generates a bit stream from the parallel bits loaded into the shift register and the generated bit stream is converted to serial bit by a multiplexer.