Invention Grant
- Patent Title: Semiconductor package with in-package compartmental shielding and fabrication method thereof
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Application No.: US16718146Application Date: 2019-12-17
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Publication No.: US10896880B2Publication Date: 2021-01-19
- Inventor: Chung-Che Tsai , Hsien-Chou Tsai
- Applicant: Shiann-Tsong Tsai , Hsien-Chou Tsai , Hsien-Wei Tsai , Yen-Mei Tsai Huang
- Applicant Address: TW Hsinchu; TW Taipei; TW Taipei; TW Taipei
- Assignee: Shiann-Tsong Tsai,Hsien-Chou Tsai,Hsien-Wei Tsai,Yen-Mei Tsai Huang
- Current Assignee: Shiann-Tsong Tsai,Hsien-Chou Tsai,Hsien-Wei Tsai,Yen-Mei Tsai Huang
- Current Assignee Address: TW Hsinchu; TW Taipei; TW Taipei; TW Taipei
- Agent Winston Hsu
- Priority: TW107142358A 20181128
- Main IPC: H01L23/552
- IPC: H01L23/552 ; H01L23/367 ; H01L23/42 ; H01L23/31

Abstract:
A semiconductor package includes a substrate. A high-frequency chip and a circuit component susceptible to high-frequency interference are disposed on a top surface of the substrate. A first ground ring is disposed on the substrate around the high-frequency chip. A first metal-post reinforced glue wall is disposed on the first ground ring to surround the high-frequency chip. A second ground ring is disposed on the top of the substrate around the circuit component. A second metal-post reinforced glue wall is disposed on the second ground ring to surround the circuit component. Mold-flow channels are disposed in the first and second metal-post reinforced glue walls. A molding compound covers at least the high-frequency chip and the circuit component. A conductive layer is disposed on the molding compound and is coupled to the first metal-post reinforced glue wall and/or the second metal-post reinforced glue wall.
Public/Granted literature
- US20200168560A1 SEMICONDUCTOR PACKAGE WITH IN-PACKAGE COMPARTMENTAL SHIELDING AND FABRICATION METHOD THEREOF Public/Granted day:2020-05-28
Information query
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