Invention Grant
- Patent Title: Semiconductor memory device including memory pillars and transistor and manufacturing method thereof
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Application No.: US16298029Application Date: 2019-03-11
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Publication No.: US10896913B2Publication Date: 2021-01-19
- Inventor: Takashi Fukushima , Junya Fujita , Toshiharu Nagumo
- Applicant: Toshiba Memory Corporation
- Applicant Address: JP Minato-ku
- Assignee: Toshiba Memory Corporation
- Current Assignee: Toshiba Memory Corporation
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2018-166834 20180906
- Main IPC: H01L27/11573
- IPC: H01L27/11573 ; H01L27/11565 ; H01L27/11578 ; H01L27/1157 ; H01L21/28
Abstract:
According to an embodiment, a semiconductor memory device includes a semiconductor substrate. The semiconductor substrate includes a first surface. A first semiconductor layer is provided on a first region of the first surface. A first transistor is provided on the first semiconductor layer. A second semiconductor layer is provided on a second region of the first surface. A second transistor is provided on the second semiconductor layer. A stacked body is provided on a third region of the first surface. The stacked body includes a plurality of conductors and a plurality of memory pillars. A first insulator is provided between the first semiconductor layer and the second semiconductor layer.
Public/Granted literature
- US20200083243A1 SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF Public/Granted day:2020-03-12
Information query
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