Systems and methods for performing phase error correction are provided. A reference clock signal and a target clock signal are received. A first value is generated based on a first amount of time between a first edge of the reference clock signal and a corresponding first edge of the target clock signal. A phase of the target clock signal is adjusted a first time based on a given amount computed using the first value. After the phase of the target clock signal is adjusted, a second value is generated based on a second amount of time between a second edge of the reference clock signal and a corresponding second edge of the target clock signal. The phase of the target clock signal is adjusted a second time based on the given amount, the first value, and the second value.