A switched-capacitor analog-to-digital converter (ADC) includes: a main digital-to-analog converter (DAC) circuit; a comparator coupled to the main DAC circuit and configured to determine whether the input to the comparator exceeds a pre-determined threshold; and a supplementary DAC circuit coupled to the main DAC circuit, wherein the switched-capacitor ADC is configured to operate in at least one of a first mode or a second mode, wherein in the first mode for measuring an offset of the switched-capacitor ADC, the supplementary DAC circuit is configured to shift a voltage at an output of the main DAC circuit by a first value having a first polarity, and wherein in the second mode for measuring a full-scale gain error of the switched-capacitor ADC, the supplementary DAC circuit is configured to shift the voltage at the output of the main DAC circuit by a second value having a second polarity opposite the first polarity.