Invention Grant
- Patent Title: Processor that includes a special store instruction used in regions of a computer program where memory aliasing may occur
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Application No.: US16543504Application Date: 2019-08-16
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Publication No.: US10901710B2Publication Date: 2021-01-26
- Inventor: Srinivasan Ramani , Rohit Taneja
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Martin & Associates, LLC
- Agent Derek P. Martin
- Main IPC: G06F9/45
- IPC: G06F9/45 ; G06F8/41 ; G06F9/30 ; G06F9/38

Abstract:
Processor hardware detects when memory aliasing occurs, and assures proper operation of the code even in the presence of memory aliasing. The processor defines a special store instruction that is different from a regular store instruction. The special store instruction is used in regions of the computer program where memory aliasing may occur. Because the hardware can detect and correct for memory aliasing, this allows a compiler to make optimizations such as register promotion even in regions of the code where memory aliasing may occur.
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