Invention Grant
- Patent Title: Semiconductor wafer dicing crack prevention using chip peripheral trenches
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Application No.: US16146374Application Date: 2018-09-28
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Publication No.: US10903120B2Publication Date: 2021-01-26
- Inventor: Arno Zechmann , Gianmauro Pozzovivo
- Applicant: Infineon Technologies Austria AG
- Applicant Address: AT Villach
- Assignee: Infineon Technologies Austria AG
- Current Assignee: Infineon Technologies Austria AG
- Current Assignee Address: AT Villach
- Agency: Murphy, Bilak & Homiller, PLLC
- Main IPC: H01L21/78
- IPC: H01L21/78 ; H01L29/04 ; H01L23/00 ; H01L29/778 ; H01L29/06 ; H01L23/544 ; H01L29/66

Abstract:
A method includes providing a semiconductor base substrate having a substantially planar growth surface and one or more preferred crystallographic cleavage planes and an epitaxial first type III-V semiconductor layer on the planar growth surface. A first trench that vertically extends from an upper surface of the first type III-V semiconductor layer is formed at least to the planar growth surface. The first trench has a first trench length direction that is antiparallel to the one or more preferred crystallographic cleavage planes.
Public/Granted literature
- US20190043757A1 Semiconductor Wafer Dicing Crack Prevention Using Chip Peripheral Trenches Public/Granted day:2019-02-07
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