A memory system includes a memory device comprising a plurality of planes and a controller suitable for controlling the memory device. The controller may include a processor suitable for determining at least one busy plane and at least one idle plane among the plurality of planes in response to a host command, and controlling the memory device such that the busy plane performs an operation associated with the host command and the idle plane performs an operation of erasing a complete dirty block in the idle plane. The busy plane and the idle plane may operate in parallel in response to control of the processor.