Invention Grant
- Patent Title: Intelligent post-packaging repair
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Application No.: US16161932Application Date: 2018-10-16
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Publication No.: US10909011B2Publication Date: 2021-02-02
- Inventor: Alan J. Wilson
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Holland & Hart LLP
- Main IPC: G06F11/20
- IPC: G06F11/20 ; G11C17/16 ; G11C17/18 ; G06F11/10 ; G06F3/06 ; G06F12/02 ; G06F11/16

Abstract:
Techniques are provided for storing a row address of a defective row of memory cells to a bank of non-volatile storage elements (e.g., fuses or anti-fuses). After a memory device has been packaged, one or more rows of memory cells may become defective. In order to repair (e.g., replace) the rows, a post-package repair (PPR) operation may occur to replace the defective row with a redundant row of the memory array. To replace the defective row with a redundant row, an address of the defective row may be stored (e.g., mapped) to an available bank of non-volatile storage elements that is associated with a redundant row. Based on the bank of non-volatile storage elements the address of the defective row, subsequent access operations may utilize the redundant row and not the defective row.
Information query