Invention Grant
- Patent Title: Processing memory accesses while supporting a zero size cache in a cache hierarchy
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Application No.: US16374667Application Date: 2019-04-03
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Publication No.: US10909035B2Publication Date: 2021-02-02
- Inventor: Brian R. Mestan
- Applicant: Apple Inc.
- Applicant Address: US CA Cupertino
- Assignee: Apple Inc.
- Current Assignee: Apple Inc.
- Current Assignee Address: US CA Cupertino
- Agency: Kowert Hood Munyon Rankin and Goetzel PC
- Agent Rory D. Rankin
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F12/0811 ; G06F12/0831 ; G06F12/0837 ; G06F9/30

Abstract:
A system and method for efficiently supporting a cache memory hierarchy potentially using a zero size cache in a level of the hierarchy. In various embodiments, logic in a lower-level cache controller or elsewhere receives a miss request from an upper-level cache controller. When the requested data is non-cacheable, the logic sends a snoop request with an address of the memory access operation to the upper-level cache controller to determine whether the requested data is in the upper-level data cache. When the snoop response indicates a miss or the requested data is cacheable, the logic retrieves the requested data from memory. When the snoop response indicates a hit, the logic retrieves the requested data from the upper-level cache. The logic completes servicing the memory access operation while preventing cache storage of the received requested data in a cache at a same level of the cache memory hierarchy as the logic.
Public/Granted literature
- US20200320004A1 PROCESSING MEMORY ACCESSES WHILE SUPPORTING A ZERO SIZE CACHE IN A CACHE HIERARCHY Public/Granted day:2020-10-08
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