Invention Grant
- Patent Title: NAND flash reset control
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Application No.: US15610815Application Date: 2017-06-01
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Publication No.: US10909051B2Publication Date: 2021-02-02
- Inventor: Timothy Canepa
- Applicant: Seagate Technology LLC
- Applicant Address: US CA Cupertino
- Assignee: Seagate Technology LLC
- Current Assignee: Seagate Technology LLC
- Current Assignee Address: US CA Cupertino
- Agency: Hall Estill Attorneys at Law
- Agent Mitchell McCarthy
- Main IPC: G06F13/16
- IPC: G06F13/16 ; G06F13/40 ; G11C16/10 ; G11C16/26

Abstract:
Method and apparatus for managing a non-volatile memory (NVM). In some embodiments, a memory module has a memory module electronics (MME) circuit configured to program data to and read data from solid-state non-volatile memory cells of the NVM. A controller is adapted to communicate commands and data to the MME circuit via an intervening data bus. The controller operates to reset the MME circuit by issuing a reset command to the MME circuit over the data bus, activating a decoupling circuit coupled between the data bus and a reference line at a reference voltage level to remove capacitance from the data bus resulting from the reset command, and subsequently sensing a voltage on the data bus. In some cases, multiple MME circuits and NVMs may be arranged on a plurality of flash dies which are concurrently reset by the controller.
Public/Granted literature
- US20180349301A1 NAND Flash Reset Control Public/Granted day:2018-12-06
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