Invention Grant
- Patent Title: Graphic processor unit topology-aware all-reduce operation
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Application No.: US16058087Application Date: 2018-08-08
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Publication No.: US10909651B2Publication Date: 2021-02-02
- Inventor: Li Zhang , Xingbo Wu , Wei Zhang , Yufei Ren
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Joseph Petrokaitis
- Main IPC: G06T1/20
- IPC: G06T1/20

Abstract:
A computer-implemented topology-aware all-reduce method for an environment including a plurality of systems is provided. Each system of the systems includes a plurality of computing modules. The computer-implemented topology-aware all-reduce method according to aspects of the invention includes locally partitioning and scattering data slices among the computing modules of each system to produce local summation results. The local summation results are copied from the computing modules to corresponding host memories of the f systems. A cross system all-reduce operation is executed among the systems to cause an exchange of the local summation results across the host memories and a determination of final summation partitions from the local summation results. The final summation partitions are copied from the host memories to the corresponding computing modules of each system. The final summation partitions are forwarded to all graphical processing units (GPUs) to cause a determination of final summation results therefrom.
Public/Granted literature
- US20200051201A1 GRAPHIC PROCESSOR UNIT TOPOLOGY-AWARE ALL-REDUCE OPERATION Public/Granted day:2020-02-13
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