Circuit designs and operating techniques for a storage device that includes, in one implementation, a memory controller configured to control a memory device including a plurality of memory blocks, each including a plurality of memory cells. The memory controller may include a memory device interface configured to perform data communication with the memory device, and a soft program controller communicatively coupled to the memory device interface and configured to count a number of iterations that an erase operation on an erase target memory block, among the plurality of memory blocks, has been suspended until the erase operation is completed, and to perform a soft program operation on the erase target memory block after the erase operation has been completed, based on the number of iterations that the erase operation on the erase target memory block has been suspended.