A method of fabricating a semiconductor device includes forming a first etching pattern structure and a second etching pattern structure on a substrate. The first cell etching pattern structure has a top surface at a level that is different from that of a top surface of the second etching pattern structure. The method further includes forming a first spacer layer on the first etching pattern structure and the second etching pattern structure. The first spacer layer covers top and lateral surfaces of the first etching pattern structure and top and lateral surfaces of the second etching pattern structure. The method further includes performing a first etching process on the first spacer layer to form a first spacer and a second spacer. The first spacer layer is fully exposed during the first etching process of the first spacer layer.