Invention Grant
- Patent Title: Wafer-level system-in-package packaging method and package structure thereof
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Application No.: US16227978Application Date: 2018-12-20
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Publication No.: US10910286B2Publication Date: 2021-02-02
- Inventor: Hailong Luo , Clifford Ian Drowley
- Applicant: Ningbo Semiconductor International Corporation
- Applicant Address: CN Ningbo
- Assignee: Ningbo Semiconductor International Corporation
- Current Assignee: Ningbo Semiconductor International Corporation
- Current Assignee Address: CN Ningbo
- Agency: Anova Law Group, PLLC
- Priority: CN201811028265 20180904
- Main IPC: H01L23/31
- IPC: H01L23/31 ; H01L21/56 ; H01L25/065 ; H01L23/00

Abstract:
Wafer-level system-in-package packaging method and package structure are provided. The method includes: forming a bonding structure, where the bonding structure includes a device wafer and a plurality of chips bonded to the device wafer, where the plurality of chips contains one or more first chips to-be-shielded; forming an encapsulation layer covering the plurality of chips; forming a trench in the encapsulation layer to surround each first chip of the one or more first chips; and forming a conductive material in the trench and on the encapsulation layer, where the conductive material includes a shielding housing, the shielding housing including a conductive sidewall formed in the trench and a conductive layer formed on a portion of the encapsulation layer above the each first chip and connected with the conductive sidewall.
Public/Granted literature
- US20200075442A1 WAFER-LEVEL SYSTEM-IN-PACKAGE PACKAGING METHOD AND PACKAGE STRUCTURE THEREOF Public/Granted day:2020-03-05
Information query
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