Invention Grant
- Patent Title: Semiconductor package having wafer-level active die and external die mount
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Application No.: US16461316Application Date: 2016-12-29
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Publication No.: US10910317B2Publication Date: 2021-02-02
- Inventor: Vipul Vijay Mehta , Eric Jin Li , Sanka Ganesan , Debendra Mallik , Robert Leon Sankman
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- International Application: PCT/US2016/069344 WO 20161229
- International Announcement: WO2018/125170 WO 20180705
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L21/48 ; H01L21/56 ; H01L21/683 ; H01L21/78 ; H01L23/31 ; H01L25/065 ; H01L23/48 ; H01L23/498 ; H01L23/14 ; H01L21/768

Abstract:
Semiconductor packages and package assemblies having active dies and external die mounts on a silicon wafer, and methods of fabricating such semiconductor packages and package assemblies, are described. In an example, a semiconductor package assembly includes a semiconductor package having an active die attached to a silicon wafer by a first solder bump. A second solder bump is on the silicon wafer laterally outward from the active die to provide a mount for an external die. An epoxy layer may surround the active die and cover the silicon wafer. A hole may extend through the epoxy layer above the second solder bump to expose the second solder bump through the hole. Accordingly, an external memory die can be connected directly to the second solder bump on the silicon wafer through the hole.
Public/Granted literature
- US20190279938A1 SEMICONDUCTOR PACKAGE HAVING WAFER-LEVEL ACTIVE DIE AND EXTERNAL DIE MOUNT Public/Granted day:2019-09-12
Information query
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