Invention Grant
- Patent Title: Silicon wafer manufacturing method
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Application No.: US16618899Application Date: 2018-06-06
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Publication No.: US10910328B2Publication Date: 2021-02-02
- Inventor: Bong-Gyun Ko , Toshiaki Ono
- Applicant: SUMCO CORPORATION
- Applicant Address: JP Tokyo
- Assignee: SUMCO CORPORATION
- Current Assignee: SUMCO CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Greenblum & Bernstein, P.L.C.
- Priority: JP2017-134916 20170710
- International Application: PCT/JP2018/021720 WO 20180606
- International Announcement: WO2019/012866 WO 20190117
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L51/00 ; H01L21/02 ; H01L23/14 ; H01L21/304 ; H01L23/492

Abstract:
Provided is a silicon wafer manufacturing method capable of reducing the warpage of the wafer occurring during a device process and allowing the subsequent processes, which have been suffered from problems due to severe warping of the wafer, to be carried out without problems and its manufacturing method. A silicon wafer manufacturing method according to the present invention is provided with calculating a target thickness of the silicon wafer required for ensuring a warpage reduction amount of a silicon wafer warped during a device process from a relationship between an amount of warpage of a silicon wafer and a thickness thereof occurring due to application of the same film stress to a plurality of silicon wafers having mutually different thicknesses; and processing a silicon single crystal ingot to thereby manufacture silicon wafers having the target thickness.
Public/Granted literature
- US20200091089A1 SILICON WAFER MANUFACTURING METHOD Public/Granted day:2020-03-19
Information query
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