- Patent Title: Stacked semiconductor chips having transistor in a boundary region
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Application No.: US16694316Application Date: 2019-11-25
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Publication No.: US10910349B2Publication Date: 2021-02-02
- Inventor: Sang Eun Lee
- Applicant: SAMSUNG ELECTRONICS CO., LTD.
- Applicant Address: KR Suwon-si
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Suwon-si
- Agency: Sughrue Mion, PLLC
- Priority: KR10-2017-0061143 20170517
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L21/00 ; H01L25/065 ; H01L25/00 ; H01L21/66 ; H01L23/528 ; H01L23/498 ; H01L23/00

Abstract:
A semiconductor package and a method for fabricating the same are provided. The semiconductor package includes a first semiconductor chip which includes a first region, a second region, and a boundary region between the first region and the second region; and a second semiconductor chip disposed on the first semiconductor chip, wherein the second semiconductor chip is overlapping the first region and a part of the boundary region, and not overlapping the second region, wherein a first circuit element is disposed in the first region and a second circuit element is disposed in the boundary region, and wherein second circuit element stress tolerance is greater than first circuit element stress tolerance.
Public/Granted literature
- US20200091117A1 STACKED SEMICONDUCTOR CHIPS HAVING TRANSISTOR IN A BOUNDARY REGION Public/Granted day:2020-03-19
Information query
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