Invention Grant
- Patent Title: Bipolar transistor semiconductor device
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Application No.: US16058123Application Date: 2018-08-08
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Publication No.: US10910484B2Publication Date: 2021-02-02
- Inventor: Kenji Sasaki , Yasuhisa Yamamoto
- Applicant: Murata Manufacturing Co., Ltd.
- Applicant Address: JP Kyoto
- Assignee: Murata Manufacturing Co., Ltd.
- Current Assignee: Murata Manufacturing Co., Ltd.
- Current Assignee Address: JP Kyoto
- Agency: Pearne & Gordon LLP
- Priority: JP2017-154054 20170809
- Main IPC: H01L29/739
- IPC: H01L29/739 ; H01L29/737 ; H01L27/082 ; H01L29/08 ; H01L29/10 ; H01L27/06 ; H01L29/417 ; H01L29/06 ; H01L29/423 ; H01L21/8252 ; H01L29/66

Abstract:
On a single-crystal semiconductor substrate with an upper surface including a first direction in which an inverted mesa step extends and a second direction in which a forward mesa step extends in response to anisotropic etching in which an etching rate depends on crystal plane orientation, a bipolar transistor including a collector layer, a base layer, and an emitter layer that are epitaxially grown, and a base wire connected to the base layer are arranged. A step is provided at an edge of the base layer, and the base wire is extended from inside to outside of the base layer in a direction intersecting the first direction in a plan view. An intersection of the edge of the base layer and the base wire has a disconnection prevention structure that makes it difficult for step-caused disconnection of the base wire to occur.
Public/Granted literature
- US20190058054A1 SEMICONDUCTOR DEVICE Public/Granted day:2019-02-21
Information query
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