A link control circuit (10) includes a plurality of hardware processing units serving as an uplink parser unit (11) configured to output, as an event, the contents of link control notified by an uplink control frame, a timer unit (12) configured to start/stop a timer and output a link event in accordance with expiration of the timer, a frame generation unit (13) configured to generate a downlink control frame containing the contents of link control, and a state management unit (15) configured to manage the state of the link in accordance with these events, and instruct the timer unit to start/stop the timer and the frame generation unit to generate the downlink control frame in accordance with the state of the link, thereby controlling connection establishment, maintenance, and disconnection of the link. Each of the hardware processing units includes a memory configured to store an externally changeable internal program describing a corresponding processing operation, and a processor configured to execute the corresponding processing operation in accordance with the internal program.