An information processing apparatus includes a plurality of processors and a plurality of links provided between the processors in a plurality of axis directions. Each of the processors includes a processor circuit, a memory, a memory controller, and an interconnect coupled to the processor circuit. The interconnect includes: a network switch configured to perform switching between the first links and a second link to its own processor; link counters provided to input links and output links of the first links and the second link respectively, the link counters being configured to count at least the number of packets passing through the input links and the output links; and a recorder configured to store count values of the link counters in the memory via the memory controller without a control by the processor circuit.