A test mode set circuit includes: a first test mode set block suitable for setting entry into a first test mode based on a clock signal and first data outputted from a non-volatile memory during a first period of a boot-up operation; and a second test mode set block suitable for setting entry into a second test mode based on the first data and second data outputted from the non-volatile memory during a second period of the boot-up operation, or setting entry into the second test mode based on a set signal generated by a combination of a command and an address during a normal operation.