Invention Grant
- Patent Title: Address translation cache invalidation in a microprocessor
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Application No.: US16417961Application Date: 2019-05-21
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Publication No.: US10915456B2Publication Date: 2021-02-09
- Inventor: Debapriya Chatterjee , Bryant Cockcroft , Larry Leitner , John A. Schumann , Karen Yokum
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Main IPC: G06F12/10
- IPC: G06F12/10 ; G06F12/02 ; G06F12/109 ; G06F12/1036

Abstract:
A method and an information handling system having a plurality of processors connected by a cross-processor network, where each of the plurality of processors preferably has a filter construct having an outgoing filter list that identifies logical partition identifications (LPIDs) that are exclusively assigned to that processor and/or an incoming filter list that identifies LPIDs on that processor and at least one additional processor in the system. In operation, if the LPID of the outgoing translation invalidation instruction is on the outgoing filter list, the address translation invalidation instruction is acknowledged on behalf of the system. If the LPID of the incoming invalidation instruction does not match any LPID on the incoming filter list, then the translation invalidation instruction is acknowledged, and if the LPID of the incoming invalidation instruction matches any LPID on the incoming filter list, then the invalidation instruction is sent into the respective processor.
Public/Granted literature
- US20200371951A1 ADDRESS TRANSLATION CACHE INVALIDATION IN A MICROPROCESSOR Public/Granted day:2020-11-26
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