Invention Grant
- Patent Title: Dynamically enabling tiling in 3D workloads
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Application No.: US16395717Application Date: 2019-04-26
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Publication No.: US10916052B2Publication Date: 2021-02-09
- Inventor: Justin DeCell , Saurabh Sharma , Subramaniam Maiyuran , Raghavendra Miyar , Jorge Garcia Pabon
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Jordan IP Law, LLC
- Main IPC: G06T17/10
- IPC: G06T17/10 ; G06T17/20 ; G06T1/20 ; G06T15/00

Abstract:
Methods, systems and apparatuses may provide for technology that determines the size of a graphics primitive, renders pixels associated with the graphics primitive on a per tile basis if the size exceeds a threshold, and renders the pixels associated with the graphics primitive in a mesh order if the size does not exceed the threshold. In one example, the technology discards state data associated with the graphics primitive in response to a completion of rendering the pixels associated with the graphics primitive in the mesh order.
Public/Granted literature
- US20200342662A1 DYNAMICALLY ENABLING TILING IN 3D WORKLOADS Public/Granted day:2020-10-29
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