Invention Grant
- Patent Title: Stage-number reduced gate on array circuit and display device
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Application No.: US16616971Application Date: 2019-11-12
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Publication No.: US10916172B2Publication Date: 2021-02-09
- Inventor: Zhixiong Jiang , Yanhong Meng
- Applicant: TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
- Applicant Address: CN Guangdong
- Assignee: TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
- Current Assignee: TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
- Current Assignee Address: CN Guangdong
- Agent Mark M. Friedman
- Priority: CN201910623575 20190711
- International Application: PCT/CN2019/117485 WO 20191112
- Main IPC: G09G3/20
- IPC: G09G3/20

Abstract:
The present disclosure provides a stage-number reduced gate driver on array (GOA) circuit and a display device. The circuit includes one or more stages of GOA sub-circuits. Each stage of GOA sub-circuits includes a gate signal input end, an original output end, one or more sub-output ends, and one or more branching devices respectively corresponding to the one or more sub-output ends. The gate signal input end and the original output end are respectively connected to a branching node. One end of the one or more branching devices is respectively connected to the branching node. Another end of the one or more branching devices is connected to the corresponding one or more sub-output ends. The present disclosure can solve the problem of excessive length of the GOA circuit in high-resolution model which is not conducive to a narrow bezel design.
Public/Granted literature
- US20210012694A1 STAGE-NUMBER REDUCED GATE ON ARRAY CIRCUIT AND DISPLAY DEVICE Public/Granted day:2021-01-14
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