Invention Grant
- Patent Title: Target row refresh mechanism capable of effectively determining target row address to effectively mitigate row hammer errors without using counter circuit
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Application No.: US16747553Application Date: 2020-01-21
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Publication No.: US10916293B1Publication Date: 2021-02-09
- Inventor: Ya-Chun Lai , Po-Hsun Wu , Jen-Shou Hsu
- Applicant: Elite Semiconductor Memory Technology Inc.
- Applicant Address: TW Hsinchu
- Assignee: Elite Semiconductor Memory Technology Inc.
- Current Assignee: Elite Semiconductor Memory Technology Inc.
- Current Assignee Address: TW Hsinchu
- Agent Winston Hsu
- Main IPC: G11C11/40
- IPC: G11C11/40 ; G11C11/406 ; G11C7/06 ; G06F12/02 ; G11C11/409

Abstract:
A target row refresh method includes: providing first table having M entries each capable of storing information of target row address; providing second table having K entries respectively capable of storing information of different/identical candidate row addresses; determining whether an input address in an input address register matches address information recorded in the first table; when not match, determining whether to update information of a target row latch by using the input address in the input address register according to a sample policy so as to determine whether to compare the input address with address information recorded in the second table to determine a target row address; and performing a target row refresh operation to refresh a memory device's row(s) adjacent to a target row corresponding to the target row address.
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