A semiconductor module according to an embodiment includes a circuit substrate, a first vertical transistor having a first main electrode pad facing and coupled to a first input interconnect pattern of the circuit substrate, and having a first gate electrode pad coupled to a first control interconnect pattern of the circuit substrate, a second vertical transistor having a fourth main electrode pad facing and coupled to a second input interconnect pattern of the circuit substrate, and having a second gate electrode pad facing and coupled to a second control interconnect pattern of the circuit substrate, a surge voltage absorbing device connecting the first and second input interconnect patterns to absorb surge voltage, and a plate member connecting a second main electrode pad of the first vertical transistor and a third main electrode pad of the second vertical transistor.