Invention Grant
- Patent Title: Recessed STI as the gate dielectric of HV device
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Application No.: US15061709Application Date: 2016-03-04
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Publication No.: US10916542B2Publication Date: 2021-02-09
- Inventor: Yi-huan Chen , Kong-Beng Thei , Fu-Jier Fan , Ker-Hsiao Huo , Kau-Chu Lin , Li-Hsuan Yeh , Szu-Hsien Liu , Yi-Sheng Chen
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L27/088 ; H01L21/8234 ; H01L29/423 ; H01L27/092 ; H01L29/10 ; H01L29/06

Abstract:
A method includes forming an isolation region extending into a semiconductor substrate, etching a top portion of the isolation region to form a recess in the isolation region, and forming a gate stack extending into the recess and overlapping a lower portion of the isolation region. A source region and a drain region are formed on opposite sides of the gate stack. The gate stack, the source region, and the drain region are parts of a Metal-Oxide-Semiconductor (MOS) device.
Public/Granted literature
- US20170194320A1 Recessed STI as the Gate Dielectric of HV Device Public/Granted day:2017-07-06
Information query
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