Invention Grant
- Patent Title: Nonvolatile semiconductor memory device and manufacturing method thereof
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Application No.: US16245271Application Date: 2019-01-11
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Publication No.: US10916559B2Publication Date: 2021-02-09
- Inventor: Masaru Kito , Hideaki Aochi , Ryota Katsumata , Akihiro Nitayama , Masaru Kidoh , Hiroyasu Tanaka , Yoshiaki Fukuzumi , Yasuyuki Matsuoka , Mitsuru Sato
- Applicant: KIOXIA CORPORATION
- Applicant Address: JP Tokyo
- Assignee: KIOXIA CORPORATION
- Current Assignee: KIOXIA CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- Priority: JP2006-086674 20060327
- Main IPC: H01L27/08
- IPC: H01L27/08 ; H01L27/11582 ; H01L21/822 ; H01L27/06 ; H01L27/105 ; H01L27/115 ; H01L27/11573 ; H01L27/11578 ; H01L27/11556 ; G11C16/04

Abstract:
A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.
Public/Granted literature
- US20190148404A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF Public/Granted day:2019-05-16
Information query
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