Invention Grant
- Patent Title: Method of forming gate spacer for nanowire FET device
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Application No.: US16435411Application Date: 2019-06-07
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Publication No.: US10916637B2Publication Date: 2021-02-09
- Inventor: Jeffrey Smith , Anton deVilliers
- Applicant: TOKYO ELECTRON LIMITED
- Applicant Address: JP Tokyo
- Assignee: TOKYO ELECTRON LIMITED
- Current Assignee: TOKYO ELECTRON LIMITED
- Current Assignee Address: JP Tokyo
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Main IPC: H01L29/00
- IPC: H01L29/00 ; H01L29/66 ; H01L29/775 ; B82Y10/00 ; H01L29/40 ; H01L29/786 ; H01L29/08 ; H01L21/02 ; H01L21/28 ; H01L29/06 ; H01L29/423

Abstract:
A method of forming a gate-all-around semiconductor device, includes providing a substrate having a layered fin structure thereon. The layered fin structure includes a channel portion and a sacrificial portion each extending along a length of the layered fin structure, wherein the layered fin structure being covered with replacement gate material. A dummy gate is formed on the replacement gate material over the layered fin structure, wherein the dummy gate having a critical dimension which extends along the length of the layered fin structure. The method further includes forming a gate structure directly under the dummy gate, the gate structure including a metal gate region and gate spacers provided on opposing sides of the metal gate region, wherein a total critical dimension of the gate structure is equal to the critical dimension of the dummy gate.
Public/Granted literature
- US20190296128A1 METHOD OF FORMING GATE SPACER FOR NANOWIRE FET DEVICE Public/Granted day:2019-09-26
Information query
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