Invention Grant
- Patent Title: Dual device semiconductor structures with shared drain
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Application No.: US16376664Application Date: 2019-04-05
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Publication No.: US10917052B2Publication Date: 2021-02-09
- Inventor: Shanjen Pan , Marc L. Tarabbia , Christian Larsen
- Applicant: Cirrus Logic International Semiconductor Ltd.
- Applicant Address: GB Edinburgh
- Assignee: Cirrus Logic International Semiconductor Ltd.
- Current Assignee: Cirrus Logic International Semiconductor Ltd.
- Current Assignee Address: GB Edinburgh
- Agency: Norton Rose Fulbright US LLP
- Main IPC: H03F3/217
- IPC: H03F3/217 ; H01L27/02 ; H01L21/8234 ; H01L29/08 ; H03F3/185 ; H03F3/187 ; H03F3/45 ; H01L49/02 ; H01L29/66 ; H01L29/06 ; H01L27/088

Abstract:
Transistors may be manufactured with a shared drain to reduce die area consumed by circuitry. In one example, two transistors can be manufactured that include two body regions that abut a shared drain region. The two transistors can be independently operated by coupling terminals to a source and a gate for each transistor and the shared drain. Characteristics of the two transistors can be controlled by adjusting feature sizes, such as overlap between the gate and the shared drain for a transistor. In particular, two transistors with different voltage requirements can be manufactured using a shared drain structure, which can be useful in amplifier circuitry and in particular Class-D amplifiers.
Public/Granted literature
- US20190238104A1 DUAL DEVICE SEMICONDUCTOR STRUCTURES WITH SHARED DRAIN Public/Granted day:2019-08-01
Information query
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