Self-adaptive termination impedance circuit
Abstract:
A memory system includes a memory device with a termination circuit providing a termination impedance for a data signal in the memory device. The device also includes a calibration circuit configured to set the termination impedance to a predetermined value. The device further includes an impedance adjustment circuit configured to adjust the termination impedance based on a feedback signal indicating a change in the termination impedance due to at least one of a change in a temperature of the memory device or a change in voltage of a voltage bus in the memory device.
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