Invention Grant
- Patent Title: Cell layout of semiconductor device
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Application No.: US16210808Application Date: 2018-12-05
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Publication No.: US10922466B2Publication Date: 2021-02-16
- Inventor: Yi-Lin Chuang , Huang-Yu Chen , Yun-Han Lee
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Maschoff Brennan
- Main IPC: G06F30/30
- IPC: G06F30/30 ; G06F30/392 ; G06F30/394 ; G06F30/398 ; G06F30/396

Abstract:
A device is disclosed that includes a cell block, at least one first metal interconnect, and second metal interconnects. The cell block includes a pin disposed at a Nth metal layer in a cell layout. The at least one first metal interconnect is disposed at a (N+1)th metal layer above the Nth metal layer and stacked over the pin, and electrically coupled to the pin. The second interconnects are disposed at a (N+2)th metal layer and stacked over the at least one first metal interconnect, and parallel to each other. The second metal interconnects are electrically coupled to the at least one first metal interconnect, and forming an equivalent tapping point of the pin of the cell block. The equivalent tapping point and the pin are vertically overlapped with each other, and fabrication of the device is initiated after a DRC or a SEM simulation test is passed.
Public/Granted literature
- US20190108302A1 CELL LAYOUT OF SEMICONDUCTOR DEVICE Public/Granted day:2019-04-11
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