Disclosed is an illustrative bit cell that includes a first inverter circuit that includes a first input node and a first output node and a second inverter circuit that includes a second input node and a second output node, wherein the first output node is coupled to the second input node and the second output node is coupled to the first input node. The bit cell also includes a first extension field effect transistor that includes a first gate structure, a first cell-internal S/D region and a first cell boundary node S/D region, wherein first cell-internal S/D region electrically terminates within the cell boundary. The first gate structure is electrically coupled to one of the first or second input nodes and it is also shorted to the first cell-internal S/D region.