A processing system includes multiple processors in which first processor operates at a first clock frequency and first supply voltage at all times. At least one processor is dynamically switchable to operate at the first clock frequency and first supply voltage resulting in the first and second processors providing symmetrical multi-processing (SMP) or at a second clock frequency and a second supply voltage resulting in the first and second processors providing asymmetrical multi-processing (ASMP). A third processor may be included that also operates at the first clock frequency and the first supply voltage at all times. Various criteria can be used to determine when to switch the at least one switchable processor to improve power consumption and/or performance. A controller enables control and fast-switching between the two modes for the switchable processor. Upon receipt of a switching command to switch between SMP and ASMP, a series or sequence of actions are performed to control a voltage supply and CPU/memory clock to the switchable processor and cache memory.